1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device equipped with an address counter using a point-shift type FIFO circuit.
2. Description of Related Art
A synchronous memory device, represented by a synchronous DRAM (Dynamic Random Access Memory), has been widely used for a main memory of a personal computer and the like. The synchronous memory device inputs or outputs data in synchronization with a clock signal supplied from a controller. Therefore, the use of a higher-speed clock leads to an increase in data transfer rate.
However, even in the synchronous DRAM, a DRAM core still operates in an analog mode, requiring a sense operation to amplify extremely weak electric charges. As a result, it is not possible to reduce the time required to output the first data after a read command is issued. Therefore, after a predetermined delay time has passed since the issuing of the read command, the first data are output in synchronization with an external clock.
The delay time in the read operation is usually referred to as “CAS latency,” and is set to the integral multiple of a clock cycle. For example, when the CAS latency is five (CL=5), the first data are output in synchronization with an external clock signal of five cycles after a read command is received in synchronization with an external clock signal. That is, five clock cycles later, the first data are output.
Such a delay is necessary even for a write operation. In the write operation, after a predetermined delay time has passed since the issuing of a write command, data need to be input sequentially in synchronization with external clock signal. The delay time in the write operation is usually referred to as “CAS write latency,” and is set to the integral multiple of a clock cycle. For example, when the CAS write latency is five (CWL=5), the first data need to be input in synchronization with an external clock signal of five clock cycles after the write command is issued in synchronization with an external clock signal.
Moreover, what is employed by a DDR2 (Double Data Rate 2) or later model SDRAM is a Posted CAS method, which enables a controller to issue to a synchronous memory device a read or write command at an earlier timing than an original issuing timing. The preceding time, i.e. the difference between the original timing at which the read or write command should be issued and the actual timing at which the read or write command is issued in advance, is referred to as additive latency (AL). Therefore, in the read operation for example, the period required to start outputting read data after the read command is issued is defined as AL+CL.
When the Posted CAS method is used, the input timing of a column address is preceded in accordance with the issuing timing of the read or write command. Therefore, the column address needs to be held inside a semiconductor device (synchronous memory device) until the additive latency has passed. For the above purpose, in a DDR2 or later model SDRAM, a FIFO circuit is used to delay an address signal by a predetermined period of time. Such a FIFO circuit is generally referred to as an “address counter.”
The simplest way to delay address signals is to input the address signals into a shift register, as well as to use a shift-register type FIFO circuit that sequentially shifts the address signals. However, according to the above method, the number of stages of the shift register required increases in proportion to latency. Therefore, the problem is that a circuit increases in scale accordingly as the latency becomes larger. The latency tends to become larger at a higher clock frequency. Thus, an increase in latency associated with the speeding up of the synchronous memory device is inevitable.
As a FIFO circuit that is smaller in scale than the shift-register type FIFO circuit, a point-shift type FIFO circuit, disclosed in Japanese Patent Application Laid-Open No. 2009-15952, is known. The point-shift type FIFO circuit includes a plurality of latch circuits which are each equipped with an input gate and an output gate, and which are connected in parallel. By electrically connecting any one of a plurality of input gates and any one of a plurality of output gates, the FIFO circuit is able to arbitrarily set a timing to output a latched address signal to a subsequent internal circuit in response to the issuing timing of a read or write command.
The number of latch circuits required for the point-shift type FIFO circuit is not equal to a value of latency, but is defined based on the maximum number of accumulated address signals to be delayed. Therefore, it is possible to make a circuit smaller in size than when a shift register is used.
In an address counter disclosed in Japanese Patent Application Laid-Open No. 2009-15952, an input pointer circuit, which generates an input pointer signal that controls a plurality of input gates, and an output pointer circuit, which generates an output pointer signal that controls a plurality of output gates, are both configured by shift-register type circuits. The shift-register type circuits are able to make a pointer change at high speed in synchronization with a clock signal. Therefore, an excellent feature of the shift-register type circuits is that noise or hazard indicative of uncertain data (uncertain address information) does not appear in an address signal that is input into or output from a latch circuit. However, the number of bits or the number of signal lines of a signal output from a shift-register type circuit becomes equal to the number of input and output gates. Therefore, a large number of signal lines is required.